1. Field of the Invention
The present invention relates generally to memory sub-systems, and more specifically, to a technique for reducing memory latency during a memory request.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In today""s complex computer systems, speed, flexibility, and reliability in timing control are issues typically considered by design engineers tasked with meeting customer requirements while implementing innovations which are constantly being developed for the computer systems and their components. Computer systems typically include a plurality of memory devices which may be used to store programs and data and may be accessible to other system components such as processors or peripheral devices. Typically, memory devices are grouped together to form memory modules, such as dual-inline memory modules (DIMMs). Computer systems may incorporate numerous modules to increase the storage capacity in the system.
Each request to memory has an associated latency period corresponding to the interval of time between the initiation of the request from a requesting device, such as a processor, and the time the requested data is delivered to the requesting device. A memory controller may be tasked with coordinating the exchange of requests and data in the system between requesting devices and each memory device such that timing parameters, such as latency, are considered to ensure that requests and data are not corrupted by overlapping requests and information.
In memory sub-systems, memory latency is a critical design parameter. Reducing latency by even one clock cycle can significantly improve system performance. In typical systems, a processor, such as a microprocessor, may initiate a read command to a memory device in the memory sub-system. During a read operation, the initiating device will deliver the read request via a processor bus. The processor address and command information from the processor bus is decoded to determine the targeted location, and in the case of a read request, the request is delivered to the memory controller. Once the command is received by the memory controller, the memory controller can issue the read command on the memory bus to the targeted memory device. Because requests from the processor may be directed to other portions of the system, such as an I/O bus, a plurality of devices such as buffers and decoders, are generally provided to intercept the delivery of requests from the processor bus such that they may be directed to the memory controller or other targeted locations, such as the I/O bus. Disadvantageously, by adding buffers and decoders along the request path to provide proper request handling, cycle latency is increased thereby slowing the overall processing speed of the request.
The present invention may address one or more of the concerns set forth above.